Today’s systems-on-chips integrate large numbers and varieties of intellectual property (IP) that come from multiple sources. Some are developed internally. Others come from one or more external suppliers. The integration of the Joint Test Action Group (JTAG) chains of these varied IP and their related controllability has proven to be a challenge that chip designers have either just accepted or have tried to address by using ad hoc solutions.
Even if the large amount of IP is developed within a single chip-design company, there is the challenge of coordinating globally dispersed teams that are each working on a piece or block of the design. Each IP comes with its own built-in self-test (BIST) solution and its own JTAG connection to the outside world.
With I/Os at a premium, test ports are particularly expensive to replicate in pad-limited designs. Chip designers have made tradeoffs by dropping some other I/O or sacrificing test coverage or IP controllability. Alternatively, they have invested engineering resources to combine these different test chains to conserve die area and reduce the number of JTAG ports.
These ad hoc IP test integration approaches are based on in-house scripting and typically rely on direct access to I/Os. This may have been a viable solution in the past when the average design had a small number of IP whose I/Os could be brought out directly at the SoC level. But with larger designs, more IP, and a limited number of I/Os, direct testing of the entire design is not an option. Standard top-down design-for-test (DFT) approaches using centralized test management or control add area while increasing design time and test costs.
One possible solution is to use a hierarchical DFT approach with a standard and unified interface that enables efficient testing of large designs without adding area or additional test costs. Such an approach enables sign-off at each design hierarchy for integration at the SoC level. As different design blocks or hierarchies are completed in various parts of the world by different teams, each team can sign off on test in the same way it would sign off on timing or any physical aspect of the design. Then, the blocks can be integrated into a single unified design.
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As design size increases, the test pattern development time and the amount of time required to test the entire SoC both increase significantly. It is not uncommon for designs to be over 100 million gates, requiring several weeks to develop chip-level test patterns. In such scenarios, it is useful to be able to reuse the test patterns at the IP or block level and then automatically port those patterns to the SoC level and test the entire SoC.
An effective hierarchical test solution should provide an area-efficient and unified framework to control and observe the many IP blocks. It also should enable IP and block-level test pattern portability to the SoC level, eliminating the need to recreate them. And, it should use a well-understood standard as the interface to the IP to enable an ecosystem of support from both IP suppliers and test solution providers.
IEEE 1500 is just such a standard. This industry-defined scalable standard architecture enables test reuse and integration for embedded cores and associated circuitry. When used in conjunction with the widely popular 1149.1 JTAG standard, it provides a convenient solution to the challenge of hierarchical SoC test.
Also known as “Standard Testability method for Embedded Core-based Integrated Circuits,” IEEE 1500 includes serial and parallel test access mechanisms (TAMs) and a rich set of instructions suitable for testing cores, SoC interconnect, and circuitry. Core test language (CTL) is the official mechanism for describing IEEE 1500 wrappers and test data associated with cores.[1]
While it explicitly claims to forego addressing analog circuits and focuses on facilitating efficient test of digital aspects of SoCs, it can be used to interface with analog and mixed-signal IP. A standard like IEEE 1500 gives users the flexibility to utilize it in test and debug environments throughout the design lifecycle.
source: http://electronicdesign.com/embedded/apply-ieee-1500-integrate-multiple-jtag-chains-socs
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