Select The Right PLL-based Oscillator For Your Timing Application

More than 10 years ago, the frequency control industry introduced PLL-based (phase-locked loop) oscillators, an innovation that pioneered several features previously unavailable with traditional crystal oscillators (XOs). Leveraging internal clock synthesizer IC technology, PLL-based XOs can be programmed to support a wide range of frequencies.

This breakthrough eliminated the material processing steps required to cut and machine quartz to make it resonate at a particular frequency. It also made it possible for PLL-based XOs to be frequency-programmed and shipped to customers with very short lead times. Given that traditional oscillator lead times can approach 14 weeks or longer, many hardware designers rushed to take advantage of programmable oscillators due to their significant lead-time benefit.

Unfortunately, significant issues arose. Some designs that had migrated from using traditional XOs to using PLL-based XOs ran into jitter-related issues that caused application-related failures ranging from excessive bit-error rates in communication links to inoperable systems-on-chip (SoCs) and processors.

These issues forced many IC suppliers to specify that PLL-based oscillators could not be used in conjunction with their devices. This turn of events made it challenging for hardware designers to take advantage of the frequency flexibility and short lead benefits offered by PLL-based oscillators. So why did this happen? It turns out that PLL technology varies widely from supplier to supplier.

A sub-optimal PLL design leads to excessive oscillator phase noise and jitter peaking (Fig. 1a). The phase jitter of this particular PLL-based XO was measured at 150 ps RMS integrated over the 12-kHz to 20-MHz band. This level of performance makes it unsuitable for clocking high-speed physical layers (PHYs), which typically require <1-ps RMS jitter references. The bimodal period jitter may be a sign of a PLL stability issue that could have a detrimental performance impact on the SoC using this XO.

source: http://electronicdesign.com/analog/select-right-pll-based-oscillator-your-timing-application

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