A significant upgrade in performance usually designates semiconductor products as part of a new generation of devices. In most cases this involves semiconductor process improvements and may include packaging refinements. Efficient Power Conversion’s (EPC) new Gen 4 eGaN FETs follows this scenario with its chipscale LGA footprint (Fig. 1a) that improves on its Gen 2 eGaN FETs (Fig. 1b). Interleaved drain and source bars of Gen 4 reduce power loop inductance while internal design virtually eliminates common source inductance. As shown in Fig. 1a, the largest devices of the Gen 4 family include a gap between the top row and bottom row solder bars.
This gap in the middle of the die enables large copper traces along with cooling vias that enhance thermal performance in the associated PCB. Fig. 2 shows a sample layout for a 2 ounce copper top layer. Using 12 mil vias with 22 mil annular rings on 1.6-mm centers helps remove the heat from the area surrounding the device as well as from the center of the transistor. This configuration also supports the use of our optimal layout power loop structure when using 4 ounces or more of copper on the inner layers.
Previously, if you wanted to increase the output current capability of a FET-based DC-DC converter, you would have to parallel multiple output power devices. Although paralleling high performance eGaN devices does provide higher output power, it also increases parts count, adding cost and complexity while reducing system power density. The Gen 4 family of eGaN FETs exhibits a significant reduction in on-resistance, (RDS(ON)), which enables high current and high power density from a single eGaN FET. Table 1 compares RDS(ON) as well as other parameters for both generations of devices.
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