DDR SDRAM technology has reached its 4th generation. The DDR4 SDRAM interface achieves a maximum data rate of 3.6Gbps per bit (i.e., clock rate of 1.8GHz).
There are four key challenges in designing the placement and routing of DDR4 SDRAM interface with multi-Gigabit transmission. The major challenges include the routing topology and termination scheme for nets with multiple receivers, routing technique to minimize crosstalk, method to mitigate the impedance discontinuity due to imperfect vias, and the method to maximize the timing margin of the data transmission.
These four challenges and the ways to overcome them are discussed in the subsequent section of this paper. The study is done by analyzing signal integrity using Mentor Graphics Hyperlynx with the import of IBIS models of Kintex UltraScale FPGA from Xilinx and DDR4 SDRAM from Micron.
Routing Technique for Multiple Receivers
With the growing size of data storage, more and more memory ICs are required to be accessed by the processor or memory controller. In the worst case condition, there could be as many as eight memory ICs (i.e., fan out) connected to the processor. The conventional way of routing (i.e., tree topology) creates the issue of trace stub which degrades the signal integrity of the transmission channel. The effect of trace stub is explained in (1), where resonant frequency or the bandwidth of the transmission line is inversely proportional to the stub length. In conventional tree topology, the trace stub is lengthened with the increase in number of receivers.
The eye diagram analysis is conducted on an address signal net in tree topology with two SDRAMs driven by an FPGA at 2.4Gbps, shown in Figure 1. A 50 ohm resistor that serves as a parallel termination, is pulled up to 0.6V (i.e., half of the power rail) to amplify the dynamic range of the signal. The total trace length from FPGA to each SDRAM is 2 inch, where a stub length of 1 inch is seen by each SDRAM.
Referring to the specification of JEDEC and Micron, with bit rate of 2.4Gbps or unit interval (UI) of 416ps, setup time and hold time with respect to clock edge must be at least 62ps and 87ps respectively. The eye diagram at address pin of the memory is shown in Figure 2. The setup time is computed between the orange circle (i.e., when left half of eye opening crosses 700mV or logic 1 threshold) and the red vertical line (i.e., clock edge at the center of the eye opening). On the other hand, the hold time is computed between red vertical line and white circle (i.e., when right half of eye opening crosses 700mV or logic 1 threshold). This eye diagram indicates the setup time of 50ps, which violates the minimum timing requirement of the memory. This timing violation causes the issue of metastability where the receiver IC misinterprets the signal and results miscommunication between driver and receiver.
The lower channel bandwidth due to trace stub attenuates the high frequency components that compose the rising and falling edges of the signal, and shrinks the eye opening at the memory. In order to overcome this problem, the conventional tree topology shall be replaced by the fly-by routing topology, shown in Figure 3. The first memory (i.e., U5) is connected to the driver (i.e., U4) with a 2 inch trace, while the second memory (i.e., U6) is cascaded to the first memory with a 1 inch trace. A parallel termination 50 ohm resistor is added at the end of the trace.
The eye diagrams at memory U5 and U6 are illustrated in Figure 4A and Figure 4B respectively. The setup time and hold time in both figures are ~150ps respectively. The memory U6 does not experience stub effect at all with fly-by topology. A large eye opening is observed at memory U5 due to the fact that the long stub experienced by it, is terminated with a 50 ohm resistor. A properly terminated stub minimizes the reflection and attenuation of the signal.
The case study is further conducted with more receivers cascaded (i.e., 4 memory ICs in total) to the net, shown in Figure 5. The longest stub (i.e., 3 inch) is seen by the first memory, while shorter stub is experienced by the subsequent cascaded memory ICs. A parallel termination 50 ohm resistor is appended at the end of the channel (i.e., the last memory IC). The setup time and hold time of minimum 140ps at each receiver summarized in Table I, meet the timing requirement of JEDEC and Micron. By applying fly-by routing technique and properly terminating an opened long stub, attenuation of signal at the receiving end is alleviated.
source: http://www.edn.com/design/pc-board/4432676/DDR4-memory-interface–Solving-PCB-design-challenges
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