Altera continues to up the technology specifications in the complex programmable logic (CPLD) market with details of its first 0.35µm four layer metal device, which it claims will support densities up to 250,000 gates.
While admitting that the large gate count designs will inevitably be small in number, Altera points out that the push to 0.35µm will reduce the size and cost of designs of much lower complexity.
“Die size reduction means more dies per wafer and assuming same defect density that impacts the cost,” said Nigel Toon, Altera’s European managing director.
As well as more than doubling the maximum achievable gate density of the present Flex 10K embedded programmable logic architecture, the new family designated Flex 10KA will run off 3.3V achieving a 70 per cent reduction in power consumption.
The first 0.35µm devices built on the four layer metal SRAM process will be available in the second half of next year.
According to Paul Hollingworth, Altera’s recent;y appointed European marketing director, projected pricing for the 50,000 gate device, the EPF10K50A ,will sell for less than 46.20 in volume by the end of 1997. “That’s less than a pound for each thousand gates,” said Hollingworth, who recently joined Altera from Asic supplier Thesys Microelectronics as part of a reorganisation at the PLD company.
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